The present invention relates to a semiconductor memory device such as a dynamic random access memory (DRAM), and more specifically to an improved sense amplifier drive circuit thereof.
In general, a DRAM stores a small electric charge in a section referred to as a memory cell, and holds an electric charge as data of logic xe2x80x9c1xe2x80x9d or data of logic xe2x80x9c0xe2x80x9d. The memory cells are arranged in an array. Any memory cell can be selected by inputting a row address and a column address externally. The row address is decoded by a row decoder to select any bit line pair, whereas the column address is decoded by a column decoder to select any word line. The memory cell is located at each intersecting point of the word lines and the bit lines.
In a data read-out operation, an arbitrary word line is activated, whereby data with a small electric charge in all the memory cells connected to the word line are read out in respective bit lines connected to the memory cells, and amplified by sense amplifiers connected to the bit lines. To amplify the data with a sense amplifier, two bit lines, i.e., a bit line pair is required because a potential of a bit line in which data is not read out is used as a reference potential.
A read-out operation includes the operations of selecting any bit line pair from a plurality of bit line pairs for which an amplifying operation has been performed by a sense amplifier, extracting data from the selected bit line pair into a global data line, further amplifying the data with a main amplifier and transmitting the data to the outside of the DRAM through an interface.
The present invention is directed, in particular, to a drive circuit of the sense amplifier, among the elements constituting a DRAM.
A typical example of a conventional sense amplifier drive circuit will be described with reference to FIG. 6. In FIG. 6, MA is a memory array that has multiple memory cells MC arranged in an array. WL is a word line, and BL106 and /BL107 are bit lines. SA101 is a CMOS sense amplifier that has an NMOS amplifier 108 having two NMOS transistors N1 and N2, and a PMOS amplifier 109 having two PMOS transistors P1 and P2. QSDN102 is an NMOS sense amplifier drive transistor, which turns on when it receives a sense amplifier activating signal SAN at the gate thereof and connects a grounding power line VSS to the source of the NMOS amplifier 108. QSDP103 is a PMOS sense amplifier drive transistor, which turns on when it receives a sense amplifier activating signal SAP at the gate thereof and connects a power line VDD of a predetermined potential to the source of the PMOS amplifier 109. Both reference numerals 104 and 105 are sense amplifier driving lines, each of which has a wiring resistance r. A plurality of CMOS sense amplifiers SA are connected in parallel to these sense amplifier driving lines 4 and 5. Hereinafter, the operations of the sense amplifier drive circuit will be described briefly.
When a word line WL is activated, a small potential of a memory cell MC connected to the word line WL is read out in one bit line of a bit line pair consisting of the bit lines BL106 and /BL107 that are precharged to the midpoint potential (potential that is a half of a predetermined potential of the power line VDD). Then, when the sense amplifier drive transistors QSDN102 and QSDP103 are turned on by the sense amplifier activating signals SAN and SAP, respectively, the sensing operation starts in the sense amplifier SA. By means of this operation, the other bit line of the bit line pair is charged to a predetermined potential by the PMOS sense amplifier drive transistor QSDP103, whereas the other bit line is discharged to a ground potential by the NMOS sense amplifier drive transistor QSDN102. By means of this operation, a small potential of a memory cell MC can be amplified. Furthermore, in this amplifying operation, the charging current flows into the sense amplifier driving line 105 and the discharging current flows into the sense amplifier driving line 104.
However, in the conventional sense amplifier drive circuits having a configuration in which the charging or the discharging current from multiple sense amplifiers SA101 concentrates on one sense amplifier driving line 104 or 105, a significant voltage drop occurs because of the wiring resistance r of the sense amplifier driving lines 104 and 105 themselves, and it takes a long time to charge and discharge the bit lines BL106 and /BL107. As a result, the data readout speed may be reduced, or data may not be read out correctly.
A cause of this problem will be described by taking the operation of the NMOS amplifier 108 side as an example. (Herein, since the PMOS amplifier 109 side is symmetrical to the NMOS amplifier 108 side with regard to the principle of the operation, description thereof will be omitted.) When a word line WL is activated and a small potential is read out from an arbitrary memory cell MC of the memory cell array MA into one bit line of a bit line pair (e.g., BL106), then sense amplifier activating signals SAP and SAN allow the sense amplifier drive transistors QSDN102 and QSDP103 to turn on, respectively, so as to activate a sense amplifier SA101, and the amplifying operation starts.
At this time, when the PMOS amplifier 109 turns on and the potential of the bit line BL106 increases, the gate potential of the NMOS transistor N2 of the NMOS amplifier 108 connected to the bit line BL106 increases. Therefore the impedance of the NMOS transistor N2 becomes low and allows more current to flow therethrough. As a result, when the current flowing from the other bit line /BL107 that makes a pair with the bit line BL106 into the sense amplifier driving line 104, i.e., the discharging current becomes higher than the current capacity of the sense amplifier drive transistor QSDN102, or when a voltage drop caused by the wiring resistance r of the sense amplifier driving line 104 is significant, a source potential (bottom potential) of the NMOS amplifier 108 rises and floats. Accordingly, a voltage Vgs between the gate and the source of the NMOS transistor N2 of the NMOS amplifier 108 becomes low, and therefore, the current capacity of the NMOS transistor N2 drops and it takes a long time to discharge. As a result, the data amplifying operation takes longer time and the read-out speed is reduced, and thus the data can not be read out correctly.
Furthermore, when some transistors among the NMOS transistors N1 and N2 of the sense amplifier SA101 have a higher threshold voltage due to non-uniformity during the manufacturing process, it becomes more difficult for these NMOS transistors to be ensured the threshold voltage because of the increase of the source potential. Therefore, the operation of turning the NMOS transistor on becomes even slower and the data read-out speed is reduced more significantly.
The reduction in the read-out speed due to floating of the source potential of the NMOS amplifier 108 can occur in the following cases. For example, the read-out speed depends on the pattern of data to be read out (which indicates in the read-out operation what data is read out in each of the multiple bit line pairs that are subjected to the read-out operation), and the speed at which the sensing operation is performed varies depending on the pattern. The pattern resulting in the lowest operation speed is to read out xe2x80x9c0xe2x80x9d from one bit line pair and data xe2x80x9c1xe2x80x9d from all of the remaining bit line pairs. More specifically, the bit line from which xe2x80x9c1xe2x80x9d is read out has a precharge potential+.V of a small voltage at the beginning of the amplifying operation. This voltage provides the gate potential for one of the NMOS transistors N1 and N2 of the sense amplifier, and discharge is performed by this transistor. On the other hand, in the bit line pair from which xe2x80x9c0xe2x80x9d is read out, discharge is performed by the transistor having the gate provided with the precharge potential serving as a reference potential. Thus, the gate voltage of the transistor for discharge is higher when xe2x80x9c1xe2x80x9d is read out. Therefore, the sense amplifier SA101 that reads out xe2x80x9c1xe2x80x9d starts the sensing operation earlier than the sense amplifier SA101 that reads out xe2x80x9c0xe2x80x9d. Then, since the source potential floats because of the discharging current, the voltage Vgs between the gate and the source of the NMOS transistor N1 or N2 of the sense amplifier SA101 that reads out xe2x80x9c0xe2x80x9d becomes lower, and thus, the current capacity decreases and it takes a long time to discharge.
As described above, when the sense amplifier driving lines 104 and 105 are common, the sense amplifier SA101 interferes with each another, which causes difficulties in speeding up the sensing operation.
Furthermore, conventionally, Japanese Laid-Open Patent Publication (Tokkai) No. 5-62461 discloses a semiconductor memory device having a configuration in which an N- and a P-channel drive transistors are provided for every two of the sense amplifiers and these drive transistors are connected to a power line having a predetermined potential and a power line having a ground potential. Even in this configuration, however, since a power line having a predetermined potential and a power line having a ground potential (sense amplifier driving lines)are also shared by the plurality of sense amplifiers, individual sense amplifiers also interfere with one another and it is difficult to speed up the sensing operation.
It is an object of the present invention to provide a semiconductor memory device in which a high-speed sensing operation is realized by minimizing interference between sense amplifiers.
In order to achieve this object, in the present invention, a plurality of sense amplifier driving lines are provided instead of one sense amplifier driving line to be shared so that the charging current to multiple sense amplifiers can be supplied dispersively via the plurality of sense amplifier driving lines, and the discharging current from the multiple sense amplifiers can be drained dispersively via the plurality of sense amplifier driving lines.
More specifically, a semiconductor memory device of the present invention includes a plurality of CMOS sense amplifiers each of which including both PMOS and NMOS transistors; a PMOS sense amplifier drive transistor that is provided for every predetermined number of the plurality of CMOS sense amplifiers, connected to sources of PMOS transistors of the corresponding predetermined number of the CMOS sense amplifiers and driven by a sense amplifier driving signal; an NMOS sense amplifier drive transistor that is provided for every predetermined number of the plurality of CMOS sense amplifiers, connected to sources of NMOS transistors of the corresponding predetermined number of the CMOS sense amplifiers and driven by another sense amplifier driving signal; multiple first power lines for supplying a given power source to the plurality of CMOS sense amplifiers through the respective PMOS sense amplifier drive transistors; and multiple second power lines for supplying another given power source to the plurality of CMOS sense amplifiers through the respective NMOS sense amplifier drive transistors.
Moreover, in the semiconductor memory device of the present invention, one PMOS and one NMOS sense amplifier drive transistors are provided for every two of the CMOS sense amplifiers.
Furthermore, in the semiconductor memory device of the present invention, each of the PMOS and the NMOS sense amplifier drive transistors is shared by every two of the CMOS sense amplifiers, and a substrate contact for connecting the first and the second power lines to a substrate is formed near one of the two CMOS sense amplifiers in an area where the sense amplifier drive transistors are not arranged.
In addition, in the semiconductor memory device of the present invention, the multiple first power lines include a first common power line extending in a column direction of the CMOS sense amplifiers and connected to each of the PMOS sense amplifier drive transistors, and multiple first independent power lines connected to the common power line. The multiple second power lines include a second common power line extending in a column direction of the CMOS sense amplifiers and connected to each of the NMOS sense amplifier drive transistors, and multiple second independent power lines connected to the common power line.
Moreover, in the semiconductor memory device of the present invention, each one of the multiple first power lines and each one of the multiple second power lines are provided for every predetermined number of the CMOS sense amplifiers; and one first and one second power lines are used exclusively for the corresponding predetermined small number of the CMOS sense amplifiers.
Furthermore, in the semiconductor memory device of the present invention, each one of the multiple first independent power lines and each one of the multiple second independent power lines are provided for every two of the CMOS sense amplifiers, and between the first independent power line and the second independent power line corresponding to any set of two CMOS sense amplifiers, a global data line to which data amplified by either one of the two CMOS sense amplifiers is output is arranged so as to extend in parallel with the first and the second independent power lines.
In addition, in the semiconductor memory device of the present invention, between the first power source and the second power line that are used exclusively for a predetermined small number of CMOS sense amplifiers, a global data line to which data amplified by any one of the predetermined number of CMOS sense amplifiers is output is arranged so as to extend in parallel with the first and the second independent power lines.
Thus, in the present invention, the charging current charged from a given power source to the CMOS sense amplifiers via the PMOS sense amplifier drive transistors is supplied using multiple first power lines. The discharging current discharged from the CMOS sense amplifiers to the given power source via the NMOS sense amplifier drive transistors is released using multiple second power lines. Therefore, concentration of the charging and the discharging currents as seen in a conventional configuration in which the sense amplifier driving line is shared can be alleviated. As a result, potential rise of each source of the PMOS transistors and the NMOS transistors constituting the CMOS sense amplifiers and interference between the sense amplifiers due to this potential rise can be suppressed effectively so that a high-speed sensing operation can be realized.
In particular, according to the present invention, sense amplifier drive transistors are shared and areas in which these transistors are not arranged can be effectively utilized to form, for example, substrate contacts for the first and the second power lines therein. Thus, extra areas for the substrate contacts and the like are unnecessary and a compact layout can be obtained.
Moreover, the present invention includes power lines used exclusively for every predetermined number of the sense amplifiers, so that charging and discharging currents to the sense amplifiers can be distributed reliably, and therefore, interference between the sense amplifiers can be further minimized and data write speed can be increased more significantly.
Furthermore, according to the present invention, a global data line is located in parallel between the first power line and the second power line so that the global data line can be shielded by these power lines. Therefore, noise caused by interference occurring between the plurality of global data lines can be reduced, so that the reliability of data read-out and write can be improved.